1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, to the improvement of an element isolating structure of a semiconductor device having a so-called filed shield isolating structure and the improvement of a method of manufacturing the field shield isolating structure.
2. Description of the Background Art
A semiconductor device comprises an integrated circuit formed of many semiconductor elements on a surface of a semiconductor substrate. Each semiconductor element on the semiconductor substrate is isolated from another semiconductor element by an element isolating region. This element isolating region is an important element for the reliability and a high degree of integration of the semiconductor device. More specifically, to assure the reliability of the semiconductor device, the element isolating region is required to completely function as an insulating and isolating region. In addition, in view of the high degree of integration, it is required to be structured in an area as small as possible. As the element isolating structure, a so-called field shield isolating structure is well-known. The field shield isolating structure is disclosed in, for example Japanese Patent Laying-Open No. 122174/1987. FIG. 3 is a sectional view of an N channel MOS (Metal-Oxide-Semiconductor) field effect transistor comprising the field shield isolating structure disclosed in this gazette. In FIG. 3, two MOS transistors 1a and 1b and one element isolating region 2 are shown. The MOS transistors 1a and 1b comprise gate oxide films 4a and 4b and gate electrodes 5a and 5b formed on the surface of a p type silicon substrate 3, respectively. In addition, each of the MOS transistors 1a and 1b comprises a pair of n.sup.+ impurity regions (source and drain) 6a and 6b formed on the surface of the P type silicon substrate 3 in a self-aligning manner to each of the gate electrodes 5a and 5b. Field shield gate oxide films 7a and 7b and field shield electrodes 8a and 8b are formed on the surface of the p type silicon substrate 3 positioned in the element isolating region 2. The peripheral surfaces of the field shield electrodes 8a and 8b are covered with insulating layers 9a and 9b. Channel stop layers 10a and 10b formed of a p.sup.+ impurity region are formed on the surface of the p type silicon substrate 3 covered with the field shield electrodes 8a and 8b. In addition, a wiring layer 11 is formed on the surface of the insulating layers 9a and 9b.
A description is given of a structure and operation of the field shield isolating structure. In the structure, as shown in FIG. 3, an MOS transistor (hereinafter referred to as a FS transistor) comprises the wiring layer 11, the field shield gate oxide films 7a and 7b, the field shield electrodes 8a and 8b and the n.sup.+ impurity regions 6a and 6a of two transistors 1a and 1b.
When the semiconductor device is operated, a predetermined voltage is applied to the wiring layer 11. Then, the electric field of the wiring layer 11 has an influence on the surface of the p type silicon substrate 3 between the n.sup.+ impurity regions 6a and 6a. When an inverted layer is formed on this region, one MOS transistor 1a and the other MOS transistor 1b are rendered to be conductive, so that an element isolating function is destroyed. The electrodes 8a and 8b prevent this inverted layer from forming. More specifically, the field shield electrodes 8a and 8b are held at the same potential as that of the p type silicon substrate 3 or the ground potential. Therefore, they dissipate the influence of the voltage from the wiring layer 11 and prevent the inverted layer from forming on the surface of the p type silicon substrate. In addition, channel stop layers 10a and 10b having a concentration higher than that of the substrate are formed on the surface of the p type silicon substrate 3. The channel stop layers 10a and 10b serve to restrain this region from being inverted to the N type conductive layer by increasing the concentration of the p type impurities. In this way, in the field shield isolating structure, a transistor structure which is always off state is constituted by the field shield gate oxide films 7a and 7b, the field shield electrodes 8a and 8b and one n.sup.+ impurity regions 6a and 6a of the MOS transistors 1a and 1b. Therefore, in order to make the element isolating function reliable using the field shield isolating structure, a voltage necessary for the FS transistor constituting the field shield isolating structure to turn on, that is, a condition of threshold voltage V.sub.TH should be set high. As shown in FIG. 3, the channel stop layers 10a and 10b are provided on the surface of the p type silicon substrate 3 to set the threshold voltage high.
Referring to FIGS. 4A to 4G, a description is given of a method of manufacturing the MOS transistor device shown in FIG. 3.
First, as shown in FIG. 4A, a thin field insulating film is formed on the main surface of a p type silicon substrate 3. Then, channel stop layers 10a and 10b of a p type impurity region with a high concentration are formed at predetermined regions. Usually, these channel stop layers 10a and 10b are formed by making ion implantation of impurities on the surface of the p type silicon substrate, using a resist pattern formed by a photolithography method as a mask. Next, a polysilicon layer is deposited to be patterned into a predetermined configuration. As a result, field shield electrodes 8a and 8b are formed.
As shown in FIG. 4B, insulating layers 9a and 9b of a silicon oxide film are formed on the surface of the electrodes 8a and 8b comprising polysilicon by heat oxidation treatment.
As shown in FIG. 4C, a silicon nitride film 13 is formed on the surface of the field insulating film 7 and the insulating layers 9a and 9b. Then, a resist 14 is applied thereto.
As shown in FIG. 4D, the resist 14 and the silicon oxide film 13 are etched away at the same etching speed. The silicon nitride film 13a is selectively left at the only region sandwiched by the electrodes 8a and 8b.
As shown in FIG. 4E, the substrate surface is treated by heat oxidation using the silicon nitride films 13a and 13b as a oxidation-proof mask. As a result, the film thickness of the insulating layers 9a and 9b surrounded by the electrodes 8a and 8b are formed thick.
As shown in FIG. 4F, the silicon nitride films 13a and 13b and the field insulating film 7 positioned beneath those films are removed by anisotropic etching. As a result, the field shield gate insulating films 7a and 7b remain only beneath the field shield electrodes 8a and 8b.
As shown in FIG. 4G, a gate oxide film 4b having the same film thickness as that of the field shield oxide films 7a and 7b is formed on the surface of the p type silicon substrate 3 sandwiched by the electrodes 8a and 8b by heated oxidation treatment. Then, a polysilicon layer is deposited and patterned on the surface of the gate oxide film 4b to form a gate electrode 5b. N.sup.+ impurity regions 6a and 6b are formed on the surface of the p type silicon substrate 3 by ion implantation, using the field shield electrodes 8a and 8b covered with the insulating layers 9a and 9b and the gate electrode 5b as masks. Then, a wiring layer 11 is formed on the surface of the p type silicon substrate and the electrodes 8a and 8b through the insulating layer.
As a result, the N channel field effect transistor having the field shield isolating structure is formed.
As described above, the conventional field shield isolating structure has the channel stop layers 10a and 10b in order to increase the threshold voltage of the FS transistor constituting this isolating structure. Meanwhile, the channel stop layers 10a and 10b have a disadvantage that a narrow channel effect is caused together with the miniaturization of the semiconductor device. The narrow channel effect is caused by the fact that the impurities of the channel stop layers 10a and 10b are diffused on the channel regions of the MOS transistors 1a and 1b. This increases an effective impurity concentration of the substrate. As a result, the threshold voltages of the MOS transistors 1a and 1b are increased. More specifically, the impurities of the channel stop layers 10a and 10b are diffused under the influence of heat treatment of several times during the manufacturing processes.
In addition, in the above-described conventional example, it is intended that the film thickness of the field shield gate oxide films 7a and 7b, to be formed thin, is made to be the same as that of the gate oxide films 4a and 4b. In this way, it is intended that radiation resistance is improved. For this reason, the channel stop layers 10a and 10b were considered to be indispensable elements to increase the threshold voltage of the FS transistor for isolating elements. Therefore, it was difficult to prevent the narrow channel effect caused by the channel stop layers 10a and 10b.